1. Field of the Invention
The present invention relates to a programmable nonvolatile memory and a semiconductor integrated circuit device and, more particularly, to a one-time programmable read only memory (OTPROM) and a semiconductor integrated circuit device with the memory embedded therein. More specifically, the present invention relates to a structure for improving data retention characteristics of such memory.
2. Description of the Background Art
In a data processing system, fixed data such as a boot loader program for starting an OS (operating system), voice data and font data are stored in a ROM (read only memory) in general. ROM includes a masked ROM whose storage contents are determined by mask interconnection in a manufacturing step and an OTPROM whose storage contents can be programmed only once. As compared with an ultraviolet ray erasable ROM (EPROM: electrically programmable ROM), the OTPROM differs in that no ultraviolet ray transparent window for erasing storage contents is provided and the storage contents can be neither erased nor rewritten.
OTPROM has advantages of allowing a user to program its storage contents according to an application purpose and to add a necessary function and of enabling the use of an inexpensive package because no high-cost ultraviolet ray radiation window for erasing the storage contents is required.
ROM needs to retain programmed data fixedly over a long period of time. When an element for accumulating electric charges in a floating gate or an insulation film to store data is used for the storage element of such an OTPROM, charge retention characteristics should be ensured. Among measures conventionally taken for guaranteeing reliability of such a ROM is improving a film quality of a gate insulating film under a floating gate.
Prior Art Document 1 (Japanese Patent Laying-Open No. 2001-015617) discloses a nonvolatile semiconductor memory device in which a memory cell is comprised of a memory transistor for storing data and a selecting transistor for connecting the memory transistor to a data line (bit line) according to a selection signal. The memory transistor is formed of a stacked gate type field effect transistor having a floating gate for accumulating charges according to storage information and a control gate formed in an upper layer above the floating gate. The selecting transistor is formed through the same manufacturing steps as those of the memory transistor, and has a control gate and a floating gate short circuited to function as a single gate MOS transistor (insulated gate type field effect transistor). A MOS transistor of a peripheral circuit has a gate formed in the same manufacturing step as that of the control gate.
According to Prior Art Document 1, in an integrated circuit device having a memory and a logic circuit formed on the same semiconductor substrate, a memory cell transistor and a transistor of the logic circuit are formed through the same manufacturing steps. A gate of a peripheral transistor of the logic circuit is formed at the same manufacturing step as that of a control gate of the memory cell transistor. In Prior Art Document 1, the peripheral transistor and the memory cell transistor are formed at the same manufacturing steps and for reducing a step between a peripheral circuit portion and a memory array portion, a floating gate electrode layer of the memory cell transistor is made thin. By connecting a control gate electrode layer to the floating gate electrode layer in the selecting transistor, the control electrode of the selecting transistor is made equivalently thick.
According to Prior Art Document 1, when a first level gate electrode film (floating gate) used as a control electrode is made thin for reducing a step between transistors in the memory array portion and the peripheral logic circuit portion, a failure, such as penetration of a metal interconnection contact through the gate electrode, occurs to deteriorate reliability. To avoid such failure, a floating gate is also formed for the selecting transistor at the same step as that of the memory transistor to form the selecting transistor into a two-layer gate structure to make the film equivalently thick. A conductive film formed at the same manufacturing step as that of the control gate of the memory transistor is electrically short-circuited to a first level gate electrode corresponding to the floating gate. The document 1 intends to improve reliability of a contact of the gate electrode of the selecting transistor by securing a sufficient gate electrode film thickness of the selecting transistor.
Prior Art Document 2 (Japanese Patent Laying-Open No. 11-017156) discloses a structure for eliminating a failure of a bit line contact to a memory cell in which a field insulating film is left in a region other than a drain opening, and an opening for a drain contact is formed by applying an etching with the field insulting film used as a mask. A contact region is opened in a self-alignment manner with an aspect ratio reduced, a bit line and a bit line contact are formed in a drain contact region with the Damascene process and a source region and a source contact are formed similarly through the Damascene process.
Prior Art Document 3 (U.S. Pat. No. 6,678,190) discloses a nonvolatile memory cell structure in which a MOS transistor having only a floating gate formed is used as a memory transistor, and the memory transistor is connected to a source line through a selecting transistor. The memory transistor is connected to a bit line. In programming, current is caused to flow between the bit line and the source line to generate channel hot electrons and inject the hot electrons into the floating gate to perform writing. In erasing, collective erasing is performed by ultraviolet ray irradiation. Prior Art Document 3 discloses the use of the nonvolatile memory as general EPROM and OTPROM.
ROM is required to stably retain stored data for a long period of time. Under a certain condition, however, data retention characteristics are deteriorated. The inventor(s) of the present invention found that the essential causes of this problem is that in a nonvolatile memory for storing data by the amount of accumulated charges, a margin for process variation such as a variation in the gate to interconnection line distance and variation in size due to mask misalignment differs between a memory cell transistor and a peripheral transistor. Specifically, in a memory cell array, a signal line (a bit line or a source line) is disposed in proximity to a memory cell transistor which accumulates electrons in a floating gate or the like. When electrons are accumulated in the floating gate, a potential of the floating gate is maintained to be not higher than a ground potential, for example. The potential of the adjacent signal line is not lower than the ground potential in normal operation. When a distance between the signal line and the floating gate is shortened, an electric field between the proximal signal line and the floating gate is enlarged to cause leakage of accumulated charges from the floating gate to the proximal signal line through charge trap levels in an interlayer insulating film, thereby deteriorating data retention characteristics. Since the charge trap level in the interlayer insulating film is produced due to a defect of the film and the presence of impurities, charge trap levels inevitably exist to some extent.
Accordingly, when a memory transistor is laid out according to the same design rule (minimum design dimensions) as that for the peripheral transistor, if due to mask misalignment in a manufacturing steps, variation in manufacturing parameters, such as deviation in overlapping between a floating gate and a proximal signal line and variation in dimension is caused to shorten a distance between the proximal signal line and the floating gate, a problem of deterioration of charge retention characteristics occurs in the memory transistor to reduce a yield and reliability even when such a problem as short-circuit does not occur in the peripheral transistor.
While Prior Art Document 1 considers the gate contact failure, it fails to consider such leakage of accumulated charges from a floating gate to a proximal or close signal line (source line).
In Prior Art Document 2, in order to form an opening for formation of drain and source contacts with high precision, an interlayer insulating film formed on a field insulating film is used as a mask. Prior Art Document 2, however, only intends to improve the contact failure and neither account for the problem of mask misalignment in the case where a source line and a bit line are disposed in proximity to the memory cell transistor nor suggests even existence of the problem of charge leakage.
Prior Art Document 3 intends to achieve reduction in cell size and step between a peripheral circuit and a memory array by connecting a single gate transistor in series to for use as a nonvolatile memory cell component. Prior Art Document 3, however, considers neither charge leakage nor charge retention characteristics.